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As the year of 4nm in semiconductor manufacturing cutting edge process 2022, Samsung 4nm is weaker than TSMC 4nm should be expected by most people. This is evident from the clear comparison of the two mobile chips, Qualcomm Snapdragon 8 Gen 1 and MediaTek Tiangui 9000, which were released not long ago, in terms of energy efficiency.
Even SemiAnalysis recently cited the test results from the domestic Geek Bay. These two chips correspond to Samsung 4nm and TSMC 4nm respectively and are relatively similar in terms of CPU IP (both are Cortex-X2, A710, A510 combinations). But the CPU on top of these two SoC chips shows a significant difference in power consumption and energy efficiency. Of course, this may not be the process of the pot, Qualcomm, and MediaTek specific design in which also accounts for a considerable proportion.
It is worth mentioning that, from multiple sources, Qualcomm is expected to list a Qualcomm Snapdragon 8 Gen 2 chip using TSMC’s 4nm process in the middle of this year – when it is a variant of Gen 1. At that time to compare Samsung and TSMC 4nm, there should be more convincing data presented.
Although we can not from the material, structure, and other micro-level to carefully compare the two foundry 4nm process, but there are still some macro data and product lines and other directions can be clear that the two significant differences.
First of all, there is a precondition that needs to be reiterated, the so-called “5nm”, “4nm” and “3nm” numbers of cutting-edge manufacturing processes do not have the practical meaning of referring to a physical size. actual meaning. This means that the 4nm process transistors, there is no dimension of 4nm, including the gate length of FinFET transistors is not really 4nm, so the numbers here only indicate the generation change of the foundry manufacturing process.
Secondly, we must also clarify a question, that is, 4nm relative to 5nm, 3nm is what kind of process positioning? Generally speaking, for the complete (full) process iteration, the process name number is evolving at a pace of 0.7 times (strictly in accordance with Moore’s Law, then, it should be √0.5). For example, after the 14nm process, the full process iteration should be 10nm (14nm x 0.7 ≈ 10nm), after 10nm is 7nm, and after 7nm is 5nm.
According to this rule evolution, after 5nm is 4nm or 3nm, in the rounding rule seems to have to shake a little. But under the convention of major foundry factories, the complete process iteration of 5nm should be 3nm. then we also default, 4nm should belong to the 5nm → 3nm transition process. Its role positioning should be similar to 8nm (10nm → 7nm transition process), 6nm (7nm → 5nm transition process).
But the actual situation has become much more complicated. For TSMC, the above rules are fully applicable. TSMC N7, N5, and N3 processes are all complete process iterations, and N6 and N4 are all transition processes, or N4 is essentially a minor revision of N5. In the case of all foundry factories 3nm process are delayed, the value of N4 is to fill the market gap in this time period.
The situation on Samsung’s side is a little different. As we’ve talked about in previous 5nm comparison articles, 5nm is not the complete process iteration on Samsung’s roadmap. Samsung’s 5LPE is the same generation evolution or modification of 7LPP. In Samsung’s subsequent adjusted marketing plan, 4LPE is the complete iteration of 7LPP. Due to the magnitude of the 5LPE evolution and the different positioning of the 4LPE in the roadmap, the roles played by the Samsung 4LPE and TSMC N4 are actually quite different.
This gives rise to the question of what criteria are used to determine the “same generation evolution” and “complete iteration” of the process? In other words, why is 5LPE a revision of 7LPP, while 4LPE is the iteration of 7LPP? Why is the N4 a transitional process, while the N3 is a definitive generation?
A relatively simple answer is: it is the foundry factory’s own decision, and the foundry factory can call it whatever it wants to call it because there is nothing realistic about numbers like 5nm and 4nm anyway. But on the current process updates, in addition to the design rules compatible or not to make a judgment, there seems to be a clear rule to find. That is, the complete iteration of the process, at least the need for the existence of a clear pitch scaling.
The so-called pitch scaling, can be simply understood as the physical size of the transistor (and interconnected metal layer) changes. For example, for FinFET transistors, the minimum fin spacing between transistors needs to vary, or the gate spacing needs to vary, in order for the process iteration to be considered.
For example, in Wikichip’s database, TSMC’s N5 process MMP (minimum metal pitch, minimum metal pitch) is 30nm, compared to the N7 process 40nm shrinkage of 0.75 times; CPP (contacted poly pitch, generally understood as gate pitch) is reduced from the previous 57nm to The CPP (contacted poly pitch, generally understood as gate pitch) is reduced from 57nm to 48nm, a reduction of 0.84 times.
Pitch scaling can thus bring about an increase in transistor density. Is it also understood that the transistor density has increased, which means that the process has been iterated? The answer is not necessarily. In fact, Samsung 5LPE also has transistor density increase compared to 7LPP; and the increase on paper is not small, Wikichip previously gave the highest transistor density achievable for 7LPP as 95.07 MTr/mm² (specifically HD high density cell library); while the UHD ultra high density cell of 5LPE can reach 126.89 MTr/mm² of transistor density.
Even with this increase in transistor density, Samsung still classifies 5LPE under the 7LPP process family (instead of counting it as a complete iteration) because 5LPE basically does not do pitch scaling. It is mainly a number of schemes called scaling booster, which also includes some adjustments at the cell level. For example, 5LPE’s UHD standard cell removes a fin… However, such a scheme actually requires material-level improvements, which have been mentioned in previous articles, so I won’t repeat them here.
4LPE compared to 7LPP is the existence of pitch scaling, although the underlying transistor-level changes are relatively small – Wikichip sources said that the 4LPE process fin pitch from 27nm to 25nm, but not officially confirmed by Samsung. In addition, the metal layer part of the M1 pitch from 40nm to 28nm, M3 pitch from 36nm to 32nm.
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